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M48T02 M48T12
5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER(R) SRAM
FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, and POWER-FAIL CONTROL CIRCUIT
s s
Figure 1. 24-pin PCDIP, CAPHATTM Package
BYTEWIDETM RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS TYPICAL CLOCK ACCURACY OF 1 MINUTE A MONTH, AT 25C SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T02: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V - M48T12: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V SELF-CONTAINED BATTERY and CRYSTAL IN THE CAPHATTM DIP PACKAGE PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 2K x 8 SRAMs
24 1
s
s
s
PCDIP24 (PC) Battery/Crystal CAPHAT
s
s
s
March 2003
Rev. 3.0
1/19
M48T02, M48T12
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. WRITE Enable Controlled, WRITE AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Checking the BOK Flag Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 11. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M48T02, M48T12
SUMMARY DESCRIPTION The M48T02/12 TIMEKEEPER (R) RAM is a 2Kb x 8 non-volatile static RAM and real time clock which is pin and functional compatible with the DS1642. A special 24-pin, 600mil DIP CAPHATTM package houses the M48T02/12 silicon with a quartz crystal and a long life lithium button cell to form a highly integrated battery backed-up memory and real time clock solution. The M48T02/12 button cell has sufficient capacity and storage life to maintain data and clock funcFigure 2. Logic Diagram
VCC
tionality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range. The M48T02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Table 1. Signal Names
A0-A10 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Output Enable WRITE Enable Supply Voltage Ground
11 A0-A10
8 DQ0-DQ7
E G W VCC VSS
W E G
M48T02 M48T12
VSS
AI01027
Figure 3. DIP Connections
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 24 1 23 2 22 3 21 4 20 5 6 M48T02 19 M48T12 18 7 17 8 16 9 15 10 11 14 12 13
AI01028
VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M48T02, M48T12
Figure 4. Block Diagram
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8 x 8 BiPORT SRAM ARRAY
A0-A10
2040 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W
BOK
G
VCC
VSS
AI01329
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG TSLD(2) VIO VCC IO PD Parameter Ambient Operating Temperature
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1
Unit C C C V V mA W
Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
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M48T02, M48T12
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M48T02 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T12 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 Unit V C pF ns V V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Testing Load Circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
Table 4. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameter(1,2) Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M48T02, M48T12
Table 5. DC Characteristics
Symbol ILI ILO(2) ICC ICC1(3) ICC2(3) VIL(4) VIH VOL VOH
Note: 1. 2. 3. 4.
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V
Min
Max 1 1 80 3 3
Unit A A mA mA mA V V V V
-0.3 2.2 IOL = 2.1mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4
Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). Outputs deselected. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.' Negative spikes of -1V allowed for up to 10ns once per Cycle.
OPERATION MODES As Figure 4, page 4 shows, the static memory array and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 7F8h-7FFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations Table 6. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD(min)(1) VSO(1) 4.75 to 5.5V or 4.5 to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X
consisting of BiPORTTM READ/WRITE memory cells. The M48T02/12 includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T02/12 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.
W X VIL VIH VIH X X
DQ0-DQ7 High Z DIN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 11 for details.
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M48T02, M48T12
READ Mode The M48T02/12 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be Figure 6. READ Mode AC Waveforms
tAVAV A0-A10 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI01330
available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
M48T02/M48T12 Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXQX READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 25 25 5 70 70 70 35 10 5 35 35 5 -70 Max -150 Min 150 150 150 75 10 5 40 40 Max -200 Min 200 200 200 80 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
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M48T02, M48T12
WRITE Mode The M48T02/12 is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
tAVAV A0-A10 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01331
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
tAVAV A0-A10 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01332B
tELEH
tEHAX
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Table 8. WRITE Mode AC Characteristics
M48T02/M48T12 Symbol Parameter(1) -70 Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ tAVWH tAVEH tWHQX WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition 60 60 5 70 0 0 50 55 0 0 30 30 5 5 25 120 120 10 Max -150 Min 150 0 0 90 90 10 10 40 40 5 5 50 140 140 10 Max -200 Min 200 0 0 120 120 10 10 60 60 5 5 60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
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M48T02, M48T12
Data Retention Mode With valid VCC applied, the M48T02/12 operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T02/12 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. The power switching circuit connects external VCC to the RAM and disconnects the battery when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 9 illustrates how a BOK check routine could be structured. For more information on a Battery Storage Life refer to the Application Note AN1012. Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA AT ANY ADDRESS
WRITE DATA COMPLEMENT BACK TO SAME ADDRESS
READ DATA AT SAME ADDRESS AGAIN
IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) YES
NO (BATTERY LOW)
NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED)
WRITE ORIGINAL DATA BACK TO SAME ADDRESS
CONTINUE
AI00607
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M48T02, M48T12
Figure 10. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS
RECOGNIZED
tDR tFB tRB DON'T CARE
tR tREC
NOTE RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
Table 9. Power Down/Up AC Characteristics
Symbol tPD tF(2) tFB(3) tR tRB tREC Parameter(1) E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time E or W at VIH before Power Up Min 0 300 10 0 1 2 Max Unit s s s s s ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol VPFD VSO tDR(3) Parameter(1,2) M48T02 Power-fail Deselect Voltage M48T12 Battery Back-up Switchover Voltage Expected Data Retention Time 10 4.2 4.3 3.0 4.5 V V YEARS Min 4.5 Typ 4.6 Max 4.75 Unit V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 25C; VCC = 0V.
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M48T02, M48T12
CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' Table 11. Register Map
Data Address D7 7FF 7FE 7FD 7FC 7FB 7FA 7F9 7F8 0 0 0 0 0 ST W R D6 D5 D4 D3 D2 Year 10 M Month Date 0 Day Hours Minutes Seconds Calibration D1 D0 10 Years 0 0 FT 0 0 Function/Range BCD Format Year Month Date Day Hours Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59
Setting the Clock The eighth bit of the control register is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (on Table 11). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (7F9-7FF) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits marked as '0' in Table 11 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the Application Note AN923, "TIMEKEEPER (R) Rolling Into the 21st Century" for information on Century Rollover.
10 Date 0 0
10 Hours 10 Minutes 10 Seconds S
Keys: S = SIGN Bit FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation) R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0'
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M48T02, M48T12
Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T02/12 is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T02/12 oscillator starts within one second. Calibrating the Clock The M48T02/12 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T02/12 is accurate within 1 minute per month at 25C without calibration. The devices are tested not to exceed 35 PPM (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. The oscillation rate of any crystal changes with temperature. Figure 11, page 14 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T02/12 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12, page 14. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration Byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits in the Control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or -2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T02/12 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Day Register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the Seconds Register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 PPM oscillator frequency error, requiring a - 10 (WR001010) to be loaded into the Calibration Byte for correction. Note: Setting or changing the Calibration Byte does not affect the Frequency Test output frequency. The device must be selected and addresses must be stable at Address 7F9 when reading the 512 Hz on DQ0. The FT Bit must be set using the same method used to set the clock: using the WRITE Bit. The LSB of the Seconds Register is monitored by holding the M48T02/12 in an extended READ of the Seconds Register, but without having the READ Bit set. The FT Bit MUST be reset to '0' for normal clock operations to resume. Note: It is not necessary to set the WRITE Bit when setting or resetting the Frequency Test Bit (FT) or the Stop Bit (ST). For more information on calibration, see the Application Note AN924, "TIMEKEEPER (R) Calibration."
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M48T02, M48T12
Figure 11. Crystal Accuracy Across Temperature
ppm 20
0
-20
-40 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C -80
-60
-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C
AI02124
Figure 12. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
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M48T02, M48T12
VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 13. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48T02, M48T12
PACKAGE MECHANICAL INFORMATION Figure 14. PCDIP24 - 24-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note: Drawing is not to scale.
Table 12. PCDIP24 - 24-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 34.29 17.83 2.29 25.15 15.24 3.05 24 Max 9.65 0.76 8.89 0.53 1.78 0.31 34.80 18.34 2.79 30.73 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.350 0.702 0.090 0.990 0.600 0.120 24 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.370 0.722 0.110 1.210 0.630 0.150 inches
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M48T02, M48T12
PART NUMBERING Table 13. Ordering Information Scheme
Example: M48T 02 -70 PC 1 TR
Device Type M48T
Supply Voltage and Write Protect Voltage 02 = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 12 = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed -70 = 100ns (M48T02/12) -150 = 150ns (M48T02/12) -200 = 200ns (M48T02/12)
Package PC = PCDIP24
Temperature Range 1 = 0 to 70C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest you.
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M48T02, M48T12
REVISION HISTORY Table 14. Document Revision History
Date July 2000 13-Jul-00 07-May-01 14-May-01 16-Jul-01 20-May-02 26-Jun-02 28-Mar-03 Rev. # 1.0 1.1 2.0 2.1 2.2 2.3 2.4 3.0 First issue tREC change (Table 9) Reformatted; temp. / voltage info. added to tables (Tables 4, 5, 7, 8, 9, 10) Note added to Clock Calibration section; table footnote correction (Table 6) Basic formatting / content changes (Figure 1, Tables 4, 5, 10) Add countries to disclaimer Add footnote to table (Table 10) v2.2 template applied; test conditions updated (Table 9) Revision Details
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M48T02, M48T12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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